;   ***************************************************************
;   * Copyright (c) 2001, Embed Inc (http://www.embedinc.com)     *
;   *                                                             *
;   * Permission to copy this file is granted as long as this     *
;   * copyright notice is included in its entirety at the         *
;   * beginning of the file, whether the file is copied in whole  *
;   * or in part and regardless of whether other information is   *
;   * added to the copy.                                          *
;   *                                                             *
;   * The contents of this file may be used in any way,           *
;   * commercial or otherwise.  This file is provided "as is",    *
;   * and Embed Inc makes no claims of suitability for a          *
;   * particular purpose nor assumes any liability resulting from *
;   * its use.                                                    *
;   ***************************************************************
;
;   This module deals with low level I/O to the I/O ports.
;
         include "hal.inc"
;
;***********************************************************************
;
;   Configuration constants.
;
lbank    equ     0           ;register bank for the local state of this module
;
;   Derived constants.
;
lbankadr equ     bankadr(lbank) ;address with local state register bank
;
;***********************************************************************
;
;   Local state.
;
.bank#v(lbank) udata

.port    code
;
;***********************************************************************
;
;   Subroutine PORT_INIT
;
;   Initialize the I/O ports as used by the rest of the system.
;
         glbsub  port_init, noregs
;
;   Enable port B weak pullups.
;
         dbankif option_reg
         movlw   b'10000000'
                 ; 1-------  disable port B passive pullups
                 ; -X------  RB0 interrupt edge select, not used
                 ; --XXXXXX  timer 0 config, will be set by module using timer 0
         movwf   option_reg
;
;   Initialize the I/O ports according to how each of the bits was declared
;   with the /INBIT and /OUTBIT preprocessor directives.
;
  ifdef porta
         dbankif porta
         movlw   val_porta
         movwf   porta
         dbankif trisa
         movlw   val_trisa
         movwf   trisa
    endif

  ifdef portb
         dbankif portb
         movlw   val_portb
         movwf   portb
         dbankif trisb
         movlw   val_trisb
         movwf   trisb
    endif

  ifdef portc
         dbankif portc
         movlw   val_portc
         movwf   portc
         dbankif trisc
         movlw   val_trisc
         movwf   trisc
    endif

  ifdef portd
         dbankif portd
         movlw   val_portd
         movwf   portd
         dbankif trisd
         movlw   val_trisd
         movwf   trisd
    endif

  ifdef porte
         dbankif porte
         movlw   val_porte
         movwf   porte
         dbankif trise
         movlw   val_trise
         movwf   trise
    endif

  ifdef portf
         dbankif portf
         movlw   val_portf
         movwf   portf
         dbankif trisf
         movlw   val_trisf
         movwf   trisf
    endif

  ifdef portg
         dbankif portg
         movlw   val_portg
         movwf   portg
         dbankif trisg
         movlw   val_trisg
         movwf   trisg
    endif
;
;   Initialize other state managed by this module.
;

         leaverest

         end